Invention Grant
- Patent Title: Heterostructure power transistor with AlSiN passivation layer
- Patent Title (中): 具有AlSiN钝化层的异质结构功率晶体管
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Application No.: US13780192Application Date: 2013-02-28
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Publication No.: US08928037B2Publication Date: 2015-01-06
- Inventor: Jamal Ramdani , Michael Murphy , John Paul Edwards
- Applicant: Power Integrations, Inc.
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Bradley J. Bereznak
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/20 ; H01L21/02

Abstract:
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.
Public/Granted literature
- US20140239309A1 Heterostructure Power Transistor With AlSiN Passivation Layer Public/Granted day:2014-08-28
Information query
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