Invention Grant
US08928064B2 Gate stack of boron semiconductor alloy, polysilicon and high-K gate dielectric for low voltage applications
有权
硼半导体合金的栅堆叠,用于低电压应用的多晶硅和高K栅极电介质
- Patent Title: Gate stack of boron semiconductor alloy, polysilicon and high-K gate dielectric for low voltage applications
- Patent Title (中): 硼半导体合金的栅堆叠,用于低电压应用的多晶硅和高K栅极电介质
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Application No.: US14030520Application Date: 2013-09-18
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Publication No.: US08928064B2Publication Date: 2015-01-06
- Inventor: Martin M. Frank , Isaac Lauer , Jeffrey W. Sleight
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L29/78

Abstract:
A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.
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