Invention Grant
- Patent Title: Diode structure and method for FINFET technologies
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Application No.: US13967888Application Date: 2013-08-15
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Publication No.: US08928083B2Publication Date: 2015-01-06
- Inventor: Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Louis J. Percello
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/66

Abstract:
A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.
Public/Granted literature
- US20140217508A1 Diode Structure and Method for FINFET Technologies Public/Granted day:2014-08-07
Information query
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