Invention Grant
US08928113B2 Layout scheme and method for forming device cells in semiconductor devices
有权
用于在半导体器件中形成器件单元的布局方案和方法
- Patent Title: Layout scheme and method for forming device cells in semiconductor devices
- Patent Title (中): 用于在半导体器件中形成器件单元的布局方案和方法
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Application No.: US13082497Application Date: 2011-04-08
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Publication No.: US08928113B2Publication Date: 2015-01-06
- Inventor: Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
- Applicant: Hsien-Yu Pan , Jung-Hsuan Chen , Shao-Yu Chou , Yen-Huei Chen , Hung-Jen Liao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L27/108 ; H01L29/94 ; H01L21/70 ; H01L27/02 ; H01L27/11 ; H01L27/118

Abstract:
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
Public/Granted literature
- US20120256235A1 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES Public/Granted day:2012-10-11
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