Invention Grant
US08928113B2 Layout scheme and method for forming device cells in semiconductor devices 有权
用于在半导体器件中形成器件单元的布局方案和方法

Layout scheme and method for forming device cells in semiconductor devices
Abstract:
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
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