Invention Grant
- Patent Title: Semiconductor device having stacked chips
- Patent Title (中): 具有堆叠芯片的半导体器件
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Application No.: US13843165Application Date: 2013-03-15
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Publication No.: US08928399B2Publication Date: 2015-01-06
- Inventor: Masaru Koyanagi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick PC
- Priority: JP2012-196392 20120906
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H03K99/00 ; G06F3/06

Abstract:
According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.
Public/Granted literature
- US20140062587A1 SEMICONDUCTOR DEVICE HAVING STACKED CHIPS Public/Granted day:2014-03-06
Information query
IPC分类: