Invention Grant
- Patent Title: Layout of memory cells
- Patent Title (中): 存储单元布局
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Application No.: US13267235Application Date: 2011-10-06
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Publication No.: US08929154B2Publication Date: 2015-01-06
- Inventor: Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
- Applicant: Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/18 ; H01L27/02 ; G11C11/412 ; G11C11/413 ; H01L27/11
Abstract:
A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
Public/Granted literature
- US20130088925A1 LAYOUT OF MEMORY CELLS Public/Granted day:2013-04-11
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