Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses the first clock signal that is delivered alongside the data. The data is read from the memory buffer using the second clock signal. A read pointer is adjusted and synchronised with the delivered first clock signal. A token is generated using the delivered first clock signal, based on the read pointer. The token represents a capacity of the memory buffer having been made available. The token is passed to the first domain and synchronised with the first clock signal. The writing of data to the memory buffer is controlled based on a comparison between the synchronised token and a previously received token.