Invention Grant
US08930752B2 Scheduler for multiprocessor system switch with selective pairing
有权
具有选择性配对的多处理器系统切换调度程序
- Patent Title: Scheduler for multiprocessor system switch with selective pairing
- Patent Title (中): 具有选择性配对的多处理器系统切换调度程序
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Application No.: US13027960Application Date: 2011-02-15
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Publication No.: US08930752B2Publication Date: 2015-01-06
- Inventor: Alan Gara , Michael Karl Gschwind , Valentina Salapura
- Applicant: Alan Gara , Michael Karl Gschwind , Valentina Salapura
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Daniel P. Morris, Esq.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/16

Abstract:
System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
Public/Granted literature
- US20120210164A1 SCHEDULER FOR MULTIPROCESSOR SYSTEM SWITCH WITH SELECTIVE PAIRING Public/Granted day:2012-08-16
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