A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield.