Invention Grant
US08930958B2 Efficient network and memory architecture for multi-core data processing
有权
高效的网络和内存架构,用于多核数据处理
- Patent Title: Efficient network and memory architecture for multi-core data processing
- Patent Title (中): 高效的网络和内存架构,用于多核数据处理
-
Application No.: US13871687Application Date: 2013-04-26
-
Publication No.: US08930958B2Publication Date: 2015-01-06
- Inventor: Mark Henrik Sandstrom
- Applicant: Mark Henrik Sandstrom
- Applicant Address: US NJ Jersey City
- Assignee: Throughputer, Inc.
- Current Assignee: Throughputer, Inc.
- Current Assignee Address: US NJ Jersey City
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F9/52 ; G06F9/54 ; G06F9/50 ; G06F9/48

Abstract:
The invention provides hardware logic based techniques for a set of processing tasks of a software program to efficiently communicate with each other while running in parallel on an array of processing cores of a multi-core data processing system dynamically shared among a group of software programs. These inter-task communication techniques comprise, by one or more task of the set, writing their inter-task communication information to a memory segment of other tasks of the set at the system memories, as well as reading inter-task communication information from their own segments at the system memories. The invention facilitates efficient inter-task communication on a multi-core fabric, without any of the communications tasks needing to know whether and at which core in the fabric any other task is executing at any given time. The invention thus enables flexibly and efficiently running any task of any program at any core of the fabric.
Public/Granted literature
- US20130239122A1 Efficient Network and Memory Architecture for Multi-core Data Processing System Public/Granted day:2013-09-12
Information query