Invention Grant
- Patent Title: SiC epitaxial wafer and semiconductor device
- Patent Title (中): SiC外延晶片和半导体器件
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Application No.: US14205792Application Date: 2014-03-12
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Publication No.: US08933464B2Publication Date: 2015-01-13
- Inventor: Johji Nishio , Tatsuo Shimizu , Chiharu Ota , Takashi Shinohe
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2013-059833 20130322
- Main IPC: H01L31/0312
- IPC: H01L31/0312 ; H01L29/16 ; H01L21/02 ; C30B29/36

Abstract:
An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.
Public/Granted literature
- US20140284619A1 SIC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE Public/Granted day:2014-09-25
Information query
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