Invention Grant
US08933488B2 Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS
有权
具有与PMOS和NMOS相同的沟道和势垒结构的异质结场场效应晶体管
- Patent Title: Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS
- Patent Title (中): 具有与PMOS和NMOS相同的沟道和势垒结构的异质结场场效应晶体管
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Application No.: US13309316Application Date: 2011-12-01
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Publication No.: US08933488B2Publication Date: 2015-01-13
- Inventor: Aneesh Nainani , Krishna Chandra Saraswat
- Applicant: Aneesh Nainani , Krishna Chandra Saraswat
- Applicant Address: US CA Palo Alto
- Assignee: The Board of Trustees of the Leland Stanford Junior Univerity
- Current Assignee: The Board of Trustees of the Leland Stanford Junior Univerity
- Current Assignee Address: US CA Palo Alto
- Agency: Crawford Maunu PLLC
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L29/10 ; H01L29/66 ; H01L29/80 ; H01L21/02 ; H01L29/51
Abstract:
In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
Public/Granted literature
- US20120138899A1 SEMICONDUCTOR APPARATUSES AND METHOD THEREFOR Public/Granted day:2012-06-07
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