Invention Grant
US08933501B2 Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device
有权
NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成方法
- Patent Title: Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device
- Patent Title (中): NAND器件中的三维NAND器件和电荷陷阱层分离和浮栅形成方法
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Application No.: US14166162Application Date: 2014-01-28
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Publication No.: US08933501B2Publication Date: 2015-01-13
- Inventor: Raghuveer S. Makala , Johann Alsmeier , Yao-Sheng Lee
- Applicant: SanDisk Technologies Inc.
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies Inc.
- Current Assignee: SanDisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/28 ; H01L21/768 ; H01L29/788 ; H01L29/792
Abstract:
A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.
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