Invention Grant
- Patent Title: Method of manufacturing vertical pin diodes
- Patent Title (中): 制造垂直pin二极管的方法
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Application No.: US14073456Application Date: 2013-11-06
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Publication No.: US08933529B2Publication Date: 2015-01-13
- Inventor: Marco Peroni , Alessio Pantellini
- Applicant: Selex Sistemi Integrati S.p.A.
- Applicant Address: IT Rome
- Assignee: Selex Sistemi Integrati S.p.A.
- Current Assignee: Selex Sistemi Integrati S.p.A.
- Current Assignee Address: IT Rome
- Agency: Marshall, Gerstein & Borun LLP
- Priority: ITTO2010A0553 20100628
- Main IPC: H01L31/102
- IPC: H01L31/102 ; H01L29/868 ; H01L29/417 ; H01L29/66
Abstract:
Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.
Public/Granted literature
- US20140061876A1 METHOD OF MANUFACTURING VERTICAL PIN DIODES Public/Granted day:2014-03-06
Information query
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