Invention Grant
- Patent Title: Method and apparatus for generating delay
- Patent Title (中): 用于产生延迟的方法和装置
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Application No.: US12754968Application Date: 2010-04-06
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Publication No.: US08933741B1Publication Date: 2015-01-13
- Inventor: Shimon Avitan , Reuven Ecker
- Applicant: Shimon Avitan , Reuven Ecker
- Applicant Address: IL Yokneam
- Assignee: Marvell Israel (M.I.S.L.) Ltd.
- Current Assignee: Marvell Israel (M.I.S.L.) Ltd.
- Current Assignee Address: IL Yokneam
- Main IPC: H03H11/26
- IPC: H03H11/26 ; H03K5/13

Abstract:
Aspects of the disclosure provide an integrated circuit having a delay element that is configured as a complementary voltage based current starved delay element. The delay element drives an output node to generate an output signal in response to an input signal received at an input node. The delay element includes a first switch transistor configured to switch on in response to the input signal satisfying a switching condition, and a second switch transistor configured to switch on in response to the input signal satisfying the switching condition. The first switch transistor drives the output node with a first current that is controlled by a first bias voltage. The second switch transistor drives the output node with a second current that is controlled by a second bias voltage. The first bias voltage and the second bias voltage are complementary. In an example, both the first switch transistor and the second switch transistor are NMOS transistors. In another example, both the first switch transistor and the second switch transistor are PMOS transistors.
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