A stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space. By storing some of the associated stacks in complementary metal oxide semiconductor (CMOS) or other volatile memory, read/write operations to only F-RAM would be obviated. As compared to an all F-RAM stack implementation, a faster, less power consuming and faster program execution time is provided. Firmware code can also be provided that will tend to concentrate the more intensive calculations to that part of the stack that is in volatile memory and minimize POP/PUSH operations to the F-RAM portion of the stack. Moreover, since only the top of the stack is maintained in volatile memory, most of it remains in F-RAM which means the application can still benefit from the high F-RAM endurance and shorter power-down times.