Invention Grant
- Patent Title: Bit set modes for a resistive sense memory cell array
- Patent Title (中): 电阻读出存储单元阵列的位设置模式
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Application No.: US13274876Application Date: 2011-10-17
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Publication No.: US08934281B2Publication Date: 2015-01-13
- Inventor: Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
- Applicant: Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
- Applicant Address: US CA Scotts Valley
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Scotts Valley
- Agency: Hall Estill Attorneys at Law
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G11C11/56 ; G11C13/00

Abstract:
Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
Public/Granted literature
- US20120033482A1 Bit Set Modes for a Resistive Sense Memory Cell Array Public/Granted day:2012-02-09
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