The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.