Invention Grant
US08935569B2 Control computer system, method for controlling a control computer system, and use of a control computer system
有权
控制计算机系统,控制计算机系统的控制方法以及控制计算机系统的使用
- Patent Title: Control computer system, method for controlling a control computer system, and use of a control computer system
- Patent Title (中): 控制计算机系统,控制计算机系统的控制方法以及控制计算机系统的使用
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Application No.: US13636091Application Date: 2011-03-18
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Publication No.: US08935569B2Publication Date: 2015-01-13
- Inventor: Lukusa Didier Kabulepa , Thorsten Ehrenberg , Daniel Baumeister
- Applicant: Lukusa Didier Kabulepa , Thorsten Ehrenberg , Daniel Baumeister
- Applicant Address: DE Frankfurt
- Assignee: Continental Teves AG & Co. OHG
- Current Assignee: Continental Teves AG & Co. OHG
- Current Assignee Address: DE Frankfurt
- Agency: Brinks Gilson & Lione
- Priority: DE102010003161 20100323; DE102010041890 20101001
- International Application: PCT/EP2011/054144 WO 20110318
- International Announcement: WO2011/117156 WO 20110929
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/16 ; G06F11/20

Abstract:
A control computer system comprising at least two modules (1, 2, 1001, 1002, 1003, 1004, 1021, 1071) which are designed to be redundant with respect to one another. The control computer system having at least one comparison unit (20, 21, 91, 92, 1011, 1012) for monitoring the synchronization state of the at least two redundant modules (1, 2, 1001, 1002, 1003, 1004, 1021, 1071) and for detecting a synchronization error at least one peripheral unit (95, 96, 1022, 1030, 1031, . . . , 1038). At least one switching matrix (21, 1013, 1063) which is set up to allow or block access to the at least two redundant modules or access to the peripheral unit (95, 96, 1022, 1030, 1031, . . . , 1038) by the at least two redundant modules, and an error-handling unit (44, 1080) which is set up to receive signals from the at least one comparison unit (20, 21, 91, 92, 1011, 1012) and to drive the at least one switching matrix (1013, 1063) in order to completely or selectively prevent access to the at least two redundant modules or access to the peripheral unit by the at least two redundant modules.
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