Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include determining that a first thread is scheduled for execution on one of two or more hyperthreads, where the first instruction thread has a first priority. Such a technique also includes determining that a second instruction thread is one of executing or scheduled for execution on another of the two or more hyperthreads, where the second instruction thread has a second priority that is less than the first priority The technique can further include preempting execution of the second instruction thread based at least in part on the second instruction thread having the second priority that is less than the first priority.