Invention Grant
US08936977B2 Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
有权
在28nm低功率/高性能技术上使用硅氧化物封装，早期晕圈和延伸注入的PMOS器件的晚期原位掺杂SiGe结
- Patent Title: Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
- Patent Title (中): 在28nm低功率/高性能技术上使用硅氧化物封装，早期晕圈和延伸注入的PMOS器件的晚期原位掺杂SiGe结
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Application No.: US13482393Application Date: 2012-05-29
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Publication No.: US08936977B2Publication Date: 2015-01-20
- Inventor: Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
- Applicant: Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
- Applicant Address: SG Singapore
- Assignee: GlobalFoundries Singapore Pte. Ltd.
- Current Assignee: GlobalFoundries Singapore Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/338
- IPC: H01L21/338
Abstract:
A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
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