Invention Grant
- Patent Title: Method of semiconductor integrated circuit fabrication
- Patent Title (中): 半导体集成电路制造方法
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Application No.: US13561263Application Date: 2012-07-30
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Publication No.: US08937006B2Publication Date: 2015-01-20
- Inventor: Minchang Liang , Chie-Iuan Lin , Yao-Kwang Wu
- Applicant: Minchang Liang , Chie-Iuan Lin , Yao-Kwang Wu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205

Abstract:
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device. The method also includes forming a step-forming-hard-mask (SFHM) on the MG stack in a predetermined area on the semiconductor substrate, performing MG recessing, depositing a MG hard mask over the semiconductor substrate and recessing the MG hard mask to fully remove the MG hard mask from the MG stack in the predetermined area.
Public/Granted literature
- US20140030880A1 Method of Semiconductor Integrated Circuit Fabrication Public/Granted day:2014-01-30
Information query
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