Invention Grant
- Patent Title: Method for forming vias in a substrate
- Patent Title (中): 在基板中形成通孔的方法
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Application No.: US13085311Application Date: 2011-04-12
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Publication No.: US08937015B2Publication Date: 2015-01-20
- Inventor: Meng-Jen Wang , Chung-Hsi Wu
- Applicant: Meng-Jen Wang , Chung-Hsi Wu
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu; Angela D. Murch
- Priority: TW96146101A 20071204
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/48

Abstract:
The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.
Public/Granted literature
- US20110189852A1 Method for Forming a Via in a Substrate and Substrate with a Via Public/Granted day:2011-08-04
Information query
IPC分类: