A method and apparatus for providing clock fault detection is presented. A first clock of a plurality of clocks on a printed circuit board (PCB) is designated as a reference clock. A reference clock counter is in communication with the reference clock, counting cycles of the reference clock. A counter is provided for each other clock of the plurality of clocks, each counter counting cycles of a respective clock. The reference clock counter and each of the counters are started at a same time. When the reference clock counter reaches a maximum count value the value of each of the counters is stored and a determination is made whether the stored values are expected values.