Invention Grant
- Patent Title: Low threshold voltage CMOS device
- Patent Title (中): 低阈值CMOS器件
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Application No.: US13327870Application Date: 2011-12-16
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Publication No.: US08941184B2Publication Date: 2015-01-27
- Inventor: Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
- Applicant: Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
- Applicant Address: US NY Armonk KY Grand Cayman
- Assignee: International Business Machines Corporation,Global Foundries, Inc.
- Current Assignee: International Business Machines Corporation,Global Foundries, Inc.
- Current Assignee Address: US NY Armonk KY Grand Cayman
- Agency: Law Offices of Ira D. Blecker, P.C.
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
Public/Granted literature
- US20130154019A1 LOW THRESHOLD VOLTAGE CMOS DEVICE Public/Granted day:2013-06-20
Information query
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