Invention Grant
US08943119B2 System and method to implement a matrix multiply unit of a broadband processor
有权
实现宽带处理器的矩阵乘法单元的系统和方法
- Patent Title: System and method to implement a matrix multiply unit of a broadband processor
- Patent Title (中): 实现宽带处理器的矩阵乘法单元的系统和方法
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Application No.: US13462648Application Date: 2012-05-02
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Publication No.: US08943119B2Publication Date: 2015-01-27
- Inventor: Craig Hansen , Bruce Bateman , John Moussouris
- Applicant: Craig Hansen , Bruce Bateman , John Moussouris
- Applicant Address: US CA Sunnyvale
- Assignee: Microunity Systems Engineering, Inc.
- Current Assignee: Microunity Systems Engineering, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: McDermott Will & Emery LLP
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F7/52 ; G06F7/533 ; G06F7/57 ; G06F7/72 ; G06F9/30 ; G06F17/15 ; G06F17/16 ; G06F7/48 ; G06F7/499

Abstract:
A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
Public/Granted literature
- US20120215826A1 SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR Public/Granted day:2012-08-23
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