Invention Grant
- Patent Title: Process for producing chip
- Patent Title (中): 生产芯片的工艺
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Application No.: US14146203Application Date: 2014-01-02
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Publication No.: US08945817B2Publication Date: 2015-02-03
- Inventor: Keiji Tomizawa , Chiaki Muraoka , Takuma Kodoi
- Applicant: Canon Kabushiki Kaisha
- Applicant Address: JP Tokyo
- Assignee: Canon Kabushiki Kaisha
- Current Assignee: Canon Kabushiki Kaisha
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2013-003477 20130111
- Main IPC: B41J2/16
- IPC: B41J2/16 ; B41J2/145

Abstract:
A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip.
Public/Granted literature
- US20140198157A1 PROCESS FOR PRODUCING CHIP Public/Granted day:2014-07-17
Information query
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