Invention Grant
- Patent Title: Wafer warpage reduction
- Patent Title (中): 晶圆翘曲减少
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Application No.: US13936254Application Date: 2013-07-08
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Publication No.: US08945971B2Publication Date: 2015-02-03
- Inventor: Chun Hsiung Tsai , Shiang-Rung Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L29/04 ; H01L21/20

Abstract:
The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.
Public/Granted literature
- US20140264345A1 WAFER WARPAGE REDUCTION Public/Granted day:2014-09-18
Information query
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