Invention Grant
- Patent Title: Stiffened semiconductor die package
- Patent Title (中): 加固半导体芯片封装
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Application No.: US14292938Application Date: 2014-06-01
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Publication No.: US08945989B2Publication Date: 2015-02-03
- Inventor: Kesvakumar V. C. Muniandy , Navas Khan Oratti Kalandar
- Applicant: Kesvakumar V. C. Muniandy , Navas Khan Oratti Kalandar
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/00 ; H01L23/367 ; H01L23/498 ; H01L21/56 ; H01L23/16 ; H01L23/538 ; H01L23/58 ; H01L23/42 ; H01L23/31
Abstract:
A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.
Public/Granted literature
- US20140302641A1 STIFFENED SEMICONDUCTOR DIE PACKAGE Public/Granted day:2014-10-09
Information query
IPC分类:
