Invention Grant
- Patent Title: Methods of forming memory arrays and semiconductor constructions
- Patent Title (中): 形成记忆阵列和半导体结构的方法
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Application No.: US13591074Application Date: 2012-08-21
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Publication No.: US08946018B2Publication Date: 2015-02-03
- Inventor: Jaydip Guha , Shyam Surthi
- Applicant: Jaydip Guha , Shyam Surthi
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/8239
- IPC: H01L21/8239 ; H01L27/102 ; H01L21/8229

Abstract:
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
Public/Granted literature
- US20140057402A1 Methods of Forming Memory Arrays and Semiconductor Constructions Public/Granted day:2014-02-27
Information query
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