Invention Grant
- Patent Title: Method for forming dummy gate
- Patent Title (中): 形成虚拟门的方法
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Application No.: US14109231Application Date: 2013-12-17
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Publication No.: US08946030B2Publication Date: 2015-02-03
- Inventor: Motoki Noro , Tai-Chuan Lin , Shinji Kawada
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Rothwell, Figg, Ernst & Manbeck, P.C.
- Priority: JP2012-275741 20121218
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/8234 ; H01L27/088 ; H01L29/49 ; H01L29/78 ; H01L21/3213 ; H01L29/66 ; H01J37/32

Abstract:
Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.
Public/Granted literature
- US20140170842A1 METHOD FOR FORMING DUMMY GATE Public/Granted day:2014-06-19
Information query
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