Invention Grant
- Patent Title: Reduced area single poly EEPROM
- Patent Title (中): 减少区域单个多层EEPROM
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Application No.: US12537086Application Date: 2009-08-06
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Publication No.: US08946805B2Publication Date: 2015-02-03
- Inventor: Jozef C. Mitros , Keith Jarreau , Pinghai Hao
- Applicant: Jozef C. Mitros , Keith Jarreau , Pinghai Hao
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Frederick J. Telecky, Jr.
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L21/28
Abstract:
A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.
Public/Granted literature
- US20100032744A1 Reduced Area Single Poly EEPROM Public/Granted day:2010-02-11
Information query
IPC分类:
