Invention Grant
US08946870B2 Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
有权
用于层叠半导体管芯的半导体器件和形成阶梯式互连层的方法
- Patent Title: Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
- Patent Title (中): 用于层叠半导体管芯的半导体器件和形成阶梯式互连层的方法
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Application No.: US13349510Application Date: 2012-01-12
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Publication No.: US08946870B2Publication Date: 2015-02-03
- Inventor: Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
- Applicant: Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/31 ; H01L21/56 ; H01L23/00 ; H01L25/03 ; H01L25/065
Abstract:
A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.
Public/Granted literature
- US20120104562A1 Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die Public/Granted day:2012-05-03
Information query
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