Invention Grant
- Patent Title: Integrated circuit package-in-package system housing a plurality of stacked and offset integrated circuits and method of manufacture therefor
- Patent Title (中): 集成电路封装包装系统，其容纳多个堆叠和偏移集成电路及其制造方法
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Application No.: US11951958Application Date: 2007-12-06
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Publication No.: US08946878B2Publication Date: 2015-02-03
- Inventor: Chee Keong Chin , Jae Hak Yee , Yu Feng Feng , Frederick Cruz Santos
- Applicant: Chee Keong Chin , Jae Hak Yee , Yu Feng Feng , Frederick Cruz Santos
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/495 ; H01L23/31 ; H01L23/00
Abstract:
An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second integrated circuits stacked in a second offset configuration, below and to the die-attach paddle; connecting the second integrated circuits and a first edge lead adjacent to the first edge; and encapsulating the first integrated circuits, second integrated circuits, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed.
Public/Granted literature
- US20090146271A1 INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM Public/Granted day:2009-06-11
Information query
IPC分类:
