Invention Grant
- Patent Title: Via in substrate with deposited layer
- Patent Title (中): 通过在具有沉积层的衬底中
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Application No.: US13556339Application Date: 2012-07-24
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Publication No.: US08946899B2Publication Date: 2015-02-03
- Inventor: Cyprian Emeka Uzoh
- Applicant: Cyprian Emeka Uzoh
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/02

Abstract:
An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.
Public/Granted literature
- US20140027922A1 VIA IN SUBSTRATE WITH DEPOSITED LAYER Public/Granted day:2014-01-30
Information query
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