Invention Grant
- Patent Title: Via structure for integrated circuits
- Patent Title (中): 集成电路通路结构
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Application No.: US13169255Application Date: 2011-06-27
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Publication No.: US08946905B2Publication Date: 2015-02-03
- Inventor: Robert P. Masleid
- Applicant: Robert P. Masleid
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood Shores
- Agency: Meyertons Hood Kivlin Kowert & Goetzel
- Agent Erik A. Heter
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522

Abstract:
An integrated circuit (IC) having a concentric arrangement of stacked vias is disclosed. The IC includes first and second pluralities of signal lines on first and second metal layers, respectively. The second metal layer is arranged between the first metal layer and a silicon layer. The IC also includes a via structure implemented in a predefined area, and connects each of the first and second pluralities of signal lines to circuitry in the silicon layer through respective first and second pluralities of vias. Each via of the first and second pluralities has a center point that extends along a vertical axis from its respective metal layer to the silicon layer. Centers of each of the second plurality of vias are closer to a perimeter of the predefined area than respective centers of any of the first plurality of vias.
Public/Granted literature
- US20120326327A1 VIA STRUCTURE FOR INTEGRATED CIRCUITS Public/Granted day:2012-12-27
Information query
IPC分类: