An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage. The input buffer further includes a bias circuit configured to generate the variable voltage responsive to a state of the input signal.