Invention Grant
- Patent Title: Method and apparatus for calibrating digital background through capacitor division and swapping for reducing capacitor mismatch effect of analog-to-digital converter
- Patent Title (中): 用于通过电容分配和交换校准数字背景的方法和装置，以减少模数转换器的电容失配效应
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Application No.: US14185950Application Date: 2014-02-21
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Publication No.: US08947275B2Publication Date: 2015-02-03
- Inventor: Jae Yoon Sim , Hwa Suk Cho
- Applicant: Postech Academy-Industry Foundation
- Applicant Address: KR Pohang-Si, Gyeongsangbuk-Do
- Assignee: Postech Academy-Industry Foundation
- Current Assignee: Postech Academy-Industry Foundation
- Current Assignee Address: KR Pohang-Si, Gyeongsangbuk-Do
- Agency: Kile Park Reed & Houtteman PLLC
- Priority: KR10-2013-0018365 20130221
- Main IPC: H03M1/06
- IPC: H03M1/06 ; H03M1/00
Abstract:
A high-quality Analog to Digital Converter (ADC) is used to calibrate a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC). The present invention is advantageous in that it can fabricate a low-power high-resolution ADC by calibrating an error attributable to a capacitor mismatch through a digital background calibration apparatus and method using a Successive Approximation Register (SAR).
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