Various embodiments relate to a degrade-resistant surge suppressor that detects and suppresses surge events. The surge suppressor includes a high impedance high pass filter, one or more series inductors, and one or more capacitor banks. The capacitor bank may include a bridge rectifier circuit having two diodes and two SCRs (Silicon-Controlled Rectifiers), or a diode bridge rectifier fed by a TRIAC (Node for Alternating Current). The surge suppressor may further include a secondary trigger device to ensure proper attenuation of surge events.