Invention Grant
US08948326B2 Circuit architecture for I/Q mismatch mitigation in direct conversion receivers
有权
直接转换接收机I / Q失配缓解的电路架构
- Patent Title: Circuit architecture for I/Q mismatch mitigation in direct conversion receivers
- Patent Title (中): 直接转换接收机I / Q失配缓解的电路架构
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Application No.: US13844759Application Date: 2013-03-15
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Publication No.: US08948326B2Publication Date: 2015-02-03
- Inventor: Haim Primo , Yosef Stein
- Applicant: Analog Devices Technology
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Technology
- Current Assignee: Analog Devices Technology
- Current Assignee Address: BM Hamilton
- Agency: Patent Capital Group
- Main IPC: H04B14/06
- IPC: H04B14/06 ; H04L25/03 ; H03D3/00 ; H03D7/16 ; H04L27/38

Abstract:
An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.
Public/Granted literature
- US20140270018A1 CIRCUIT ARCHITECTURE FOR I/Q MISMATCH MITIGATION IN DIRECT CONVERSION RECEIVERS Public/Granted day:2014-09-18
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