Invention Grant
- Patent Title: Modeling gate transconductance in a sub-circuit transistor model
- Patent Title (中): 在子电路晶体管模型中建模门跨导
-
Application No.: US13194644Application Date: 2011-07-29
-
Publication No.: US08949083B2Publication Date: 2015-02-03
- Inventor: Jia Feng , Zhi-Yuan Wu , Juhi Bansal , Srinath Krishnan
- Applicant: Jia Feng , Zhi-Yuan Wu , Juhi Bansal , Srinath Krishnan
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.
Public/Granted literature
- US20130030774A1 Modeling Gate Transconductance in a Sub-Circuit Transistor Model Public/Granted day:2013-01-31
Information query
