Disclosed herein is a signal processing apparatus including: an input block receiving the predetermined number of items of data and a first enable signal taking an active state in an interval where data is valid in synchronization with a first clock; a count block counting the number of clocks in an interval where the first enable signal is inactive; an enable signal control block putting a second enable signal in an active state for the number of clocks equal to a predetermined number and putting the second enable signal in an inactive state for the number of clocks counted by the count block; an enable signal output block outputting the second enable signal; and a data output block outputting the predetermined number of items of data in synchronization with the second clock in an interval where the second enable signal is active.