Invention Grant
US08949699B1 Circuit for forward error correction encoding of data blocks across multiple data lanes
有权
用于跨多个数据通道的数据块的前向纠错编码的电路
- Patent Title: Circuit for forward error correction encoding of data blocks across multiple data lanes
- Patent Title (中): 用于跨多个数据通道的数据块的前向纠错编码的电路
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Application No.: US13598548Application Date: 2012-08-29
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Publication No.: US08949699B1Publication Date: 2015-02-03
- Inventor: Mark A. Gustlin
- Applicant: Mark A. Gustlin
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent LeRoy D. Maunu
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
In one embodiment, a method for communicating a sequence of data bits is provided. FEC coding is performed on a received sequence of data bits to produce an FEC coded sequence formatted for a first set of N data lanes. The FEC coded sequence includes FEC data blocks, in which each FEC data block has a plurality of data symbols. Alignment markers are added to the FEC coded sequence and the FEC coded sequence is multiplexed to produce a multiplexed sequence formatted for a second set of M data lanes. The multiplexing is performed only at boundaries between the data symbols or the alignment markers. The multiplexed sequence is transmitted on M data lanes.
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