Invention Grant
US08951351B2 Wafer processing hardware for epitaxial deposition with reduced backside deposition and defects
有权
用于外延沉积的晶片处理硬件具有减少的背面沉积和缺陷
- Patent Title: Wafer processing hardware for epitaxial deposition with reduced backside deposition and defects
- Patent Title (中): 用于外延沉积的晶片处理硬件具有减少的背面沉积和缺陷
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Application No.: US11868289Application Date: 2007-10-05
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Publication No.: US08951351B2Publication Date: 2015-02-10
- Inventor: Kailash Kiran Patalay , Craig Metzner , Jean Vatus
- Applicant: Kailash Kiran Patalay , Craig Metzner , Jean Vatus
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Moser Toboada
- Agent Alan Toboada
- Main IPC: C23C16/00
- IPC: C23C16/00 ; C23F1/00 ; H01L21/306 ; C23C16/458 ; C23C16/455 ; H01L21/687

Abstract:
Methods and apparatus for reducing autodoping and backside defects on a substrate during epitaxial deposition processes are provided herein. In some embodiments, an apparatus for reducing autodoping and backside defects on a substrate includes a substrate support ring having a substrate holder structure configured to support the substrate in a position for processing along an edge defined by the backside of the substrate and a sidewall of the substrate or along a plurality of discrete points on or proximate to the edge; and a spacer ring for positioning the substrate support ring above a susceptor plate to define a substrate gap region between the susceptor plate and the backside of the substrate, the spacer ring comprising a plurality of openings formed therethrough that facilitate passage of a gas into and out of the substrate gap region.
Public/Granted literature
- US20080066684A1 WAFER PROCESSING HARDWARE FOR EPITAXIAL DEPOSITION WITH REDUCED BACKSIDE DEPOSITION AND DEFECTS Public/Granted day:2008-03-20
Information query
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