Invention Grant
- Patent Title: Defect free deep trench method for semiconductor chip
- Patent Title (中): 半导体芯片无缺陷深沟法
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Application No.: US13162873Application Date: 2011-06-17
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Publication No.: US08951833B2Publication Date: 2015-02-10
- Inventor: Kun-Yi Liu
- Applicant: Kun-Yi Liu
- Applicant Address: US WA Camas
- Assignee: WaferTech, LLC
- Current Assignee: WaferTech, LLC
- Current Assignee Address: US WA Camas
- Agency: Duane Morris LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/311 ; B81C1/00 ; H01L23/58 ; H01L21/28 ; H01L21/50 ; H01L21/304

Abstract:
A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
Public/Granted literature
- US20120322259A1 DEFECT FREE DEEP TRENCH METHOD FOR SEMICONDUCTOR CHIP Public/Granted day:2012-12-20
Information query
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