Invention Grant
- Patent Title: Non-volatile memory (NVM) and logic integration
- Patent Title (中): 非易失性存储器(NVM)和逻辑集成
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Application No.: US13780591Application Date: 2013-02-28
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Publication No.: US08951863B2Publication Date: 2015-02-10
- Inventor: Mark D. Hall , Frank K. Baker, Jr. , Mehul D. Shroff
- Applicant: Mark D. Hall , Frank K. Baker, Jr. , Mehul D. Shroff
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Joanna G. Chiu; James L. Clingan, Jr.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/82 ; H01L29/423 ; H01L29/788

Abstract:
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.
Public/Granted literature
- US20130267072A1 NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION Public/Granted day:2013-10-10
Information query
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