Invention Grant
- Patent Title: Method of manufacturing a semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US14139991Application Date: 2013-12-24
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Publication No.: US08951869B2Publication Date: 2015-02-10
- Inventor: Keisuke Tsukamoto , Tatsuyoshi Mihara
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2013-025007 20130212
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/8239 ; H01L21/28 ; H01L21/285 ; H01L27/115 ; H01L29/423 ; H01L29/66 ; H01L29/788 ; H01L29/51

Abstract:
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.
Public/Granted literature
- US20140227843A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2014-08-14
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