Invention Grant
US08951915B2 Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
有权
用于制造芯片布置的方法，用于制造芯片封装的方法，芯片封装和芯片布置
- Patent Title: Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
- Patent Title (中): 用于制造芯片布置的方法，用于制造芯片封装的方法，芯片封装和芯片布置
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Application No.: US13609306Application Date: 2012-09-11
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Publication No.: US08951915B2Publication Date: 2015-02-10
- Inventor: Reinhard Hess , Katharina Umminger , Gabriel Maier , Markus Menath , Gunther Mackh , Hannes Eder , Alexander Heinrich
- Applicant: Reinhard Hess , Katharina Umminger , Gabriel Maier , Markus Menath , Gunther Mackh , Hannes Eder , Alexander Heinrich
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
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