A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.