A semiconductor device includes a p-type well region 3 and an n+ source region 4, both formed selectively in the surface portion of n− drift region 2. A trench 6 is in contact with n+ source region 4 and extends through p-type well region 3 into n− drift region 2. A field plate 8 is formed in trench 6, with a first insulator film 7 being interposed between the trench 6 surface and field plate 8. A gate electrode 10 is formed in trench 6 above field plate 10, with a second insulator film 9 being interposed between the trench 6 surface and gate electrode 10. An n−− lightly doped region 21 in n− drift region 2 crosses under the bottom of trench 6.